Embedding fonts in pdfs created with Sharelatex or Overleaf

There are those who followers of Latex (the typesetting language and tool) and are familiar with the ins and outs of everything the language and the various tools can do. Unfortunately I am not one of them. I am a noob and my only experience with the language has been through a couple of conference papers that I have typeset on sharelatex and overleaf. By the way the two platforms have joined forces now

On both of these platforms what has stumped me always is the “embedded fonts problem“. Now there are many different reasons and many different solutions, none of which worked for me initially, or maybe I did not try hard enough.

Lately though, when I generate a pdf on overleaf, I am not facing any problems, as long as the images I have included are eps and if the images themselves are pdfs, then it has helped that I have generated most of them using www.lucidchart.com, which does not create a problem with the embedded fonts. They do have a free account

My guess is that the problems I faced with fonts were due to the image pdfs being generated through Microsoft Visio using some proprietary fonts.

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Embedding fonts in pdfs created with Sharelatex or Overleaf

Rotate floats in Latex

When I was writing my thesis, there were those one-off instances, when I had a really large table with lots of columns, that I had to include. I was not really inclined to tweak around the column widths, as I would have if I was writing a paper, and I also did not have to worry about the total length.

In such a scenario, the best way out is to use rotated tables.

Here is how it is done-

\usepackage[counterclockwise,figuresright]{rotating}

to be included in the header of the tex document. This ensures that all my tables are rotated counter-clockwise. Useful when you are reading pdfs. I am also not a fan of figures rotated  in different directions based on odd or even pages.

Next comes the actual table. This part is very simple

\begin{sidewaystable} %%% LOOK HERE %%%
   \renewcommand*{\arraystretch}{1.1}
    \centering
    \caption{Performance comparison of binary trie and Enhanced Compact trie with epsilon links ($P_{trie}$ = 2) for various routing tables }
    \label{table:mem_n_lat_bt_ct}
    \begin{tabular}{
       |P{0.08\textwidth}|
        P{0.16\textwidth}|
        P{0.16\textwidth}|
        P{0.11\textwidth}|
        P{0.11\textwidth}|
        P{0.11\textwidth}|
        P{0.11\textwidth}|
       }
       \hline
       \multirow{2}{*}{\centering{Table}} & 
       \multicolumn{2}{P{0.32\textwidth}|}{Number of Nodes(k) / Total Memory (Mbits)} & 
       \multicolumn{2}{P{0.22\textwidth}|}{Trie density (\%) } & 
       \multicolumn{2}{P{0.22\textwidth}|}{Median number of PM stages} \\ 
       & $Btrie$ & $E-Ctrie_\epsilon$ & $Btrie$ & $E-Ctrie_\epsilon$ & $Btrie$ & $E-Ctrie_\epsilon$ \\ \hline
       \rowcolor{colSml}
       CAI & 16.2/ 0.6 & 5.8/ 0.3 & 19.6 & 51.5 & 25 & 24 \\ \hline 
       \rowcolor{colSml}
       SDB & 28.8/ 1.1 & 11.3/ 0.6 & 19.3 & 46.7 & 25 & 23 \\ \hline 
       \rowcolor{colSml}
       MAN & 41.3/ 1.7 & 20.8/ 1.2 & 15.2 & 29.5 & 25 & 23 \\ \hline 
       \rowcolor{colMed}
       LYS & 198.8/ 8.7 & 88.3/ 5.8 & 22.3 & 48.1 & 25 & 23 \\ \hline 
       \rowcolor{colMed}
       DXB & 279.8/ 12.9 & 116.8/ 7.6 & 22.9 & 51.8 & 25 & 24 \\ \hline 
       \rowcolor{colMed}
       MGM & 460.7/ 21.2 & 183.7/12.2 & 20.8 & 49.8 & 25 & 23 \\ \hline 
       \rowcolor{colLrg}
       IAD & 1517.7/ 75.9 & 540.5/38.2 & 25.6 & 66.5 & 25 & 25 \\ \hline 
       \rowcolor{colLrg}
       FRA & 1589.2/ 79.5 & 561.9/39.6 & 25.7 & 67.1 & 25 & 25 \\ \hline 
       \rowcolor{colLrg}
       PAO & 2453.4/127.6 & 808.2/56.4 & 25.6 & 70.9 & 25 & 25 \\ \hline 
    \end{tabular}
\end{sidewaystable}  %%% LOOK HERE %%%

The \begin{sidewaystable} and \end{sideways} command I have used have been commented with a LOOK HERE statement.

The actual table has a few other things happening within, but that is for another discussion.

Rotate floats in Latex

binding offset in latex

Laying out my thesis and realised that the geometry package in latex \LaTex&s=0$ actually has a ‘bindingoffset’ option, which is added to the left or right margin value depending on whether the page is odd or even in a two-sided document to produce the actual offset for the body text.

bindingoffset

Will I ever print and bind my thesis? No

Will anybody else do that for their reference? No

Will the University library do it for their repository? No

Well then I do not need that option.

binding offset in latex

Verilog sensitivity

A characteristic of Hardware Description Languages(HDL) (either VHDL or Verilog) is their model of a Flip Flop or a Latch. This is also called as the event control structure by the Verilog LRM. This is a structure that is not available in other programming languages that are not event driven.

The structure has a sensitivity list which indicates the signals that would trigger the actions described in the structure.  The actions modify the value/state of one or more signals and there could be different actions based on the value of other signals in the system. The conditions could use some of the signals specified in the sensitivity list. Now all this may sound very confusing, but people in the trade generally use or come across these constructs countless times.

In verilog the structure when used to describe a F/F is written as


always @(posedge clk or negedge rst_n)
begin
	if (~rst_n)
	begin
		a<= 1'b0;
		b <= 5'b00000;
	end
	else if ((en == 1'b1) && (c == 4'b0101))
	begin
		a <= 1'b1;
		b <= 5'b10101;
	end
	else
	begin
		a<= 1'b0;
		b <= 5'b00000;
	end
end

Now an interesting consideration here is that for signals that are in the sensitivity list, the value that is used to test within the conditions such as

 if (~rst_n) 

is the value that the rst_n signal takes after the event control block is triggered.

However the value of the signal ‘c’ that is used in the test condition is the one that it has “setup time” before the trigger occurs and not the value of ‘c’ after the trigger. Thus if ‘c’ is changing in a separate event control block from 4’b0010 to 4’b0101 on the same clock edge that the above event control block is triggered, then the second condition would not be evaluated to ‘true’. Instead it will continue using the old value of ‘c’. If ‘en’ remains high for one more clock cycle, then the new value of ‘c’ (4’b0101) would be used and the value of the signals ‘a’ and ‘b’ would change to 1’b1 and 5’b10101 on the next clock edge.

Now personally I find the response of the event control structure to changes in ‘c’ in accordance with real hardware. This is because in a real device, if ‘c’ is changing on a certain clock edge, then the new value would be available to the destination F/F only after a certain finite time. This time is the total of the clock-to-Q of the source F/F and the propagation delay of the wire from source to destination F/F. And taking into consideration this delay and the clock skew, in most cases, it is not possible for the new value of ‘c’ to be available before the setup time of the destination F/F.

This is an interesting behaviour that is difficult to get your head around. However once you manage to understand this correctly, working with HDLs becomes a lot easier.

 

Verilog sensitivity

How to in Verilog : pass a filename to be `included in the code using a parameter

Is there any way to pass a parameter to `include? I’m trying to do the
following

parameter DEFFILE = “file.txt”;

`include DEFFILE;

This gives me errors though…. Anyone have any ideas?

Unfortunately there does not seem to be a solution for this issue. This is because in Verilog, the `include is handled by the pre-preocessor which parses the files even before the compiler can have a go at it. The parameter on the other hand are examined during elaboration. 😦

This discussion was originally found at http://compgroups.net/comp.lang.verilog/pass-parameter-to-include/2118239. It was noticed because I was also trying to do something similar. Will update this post, when I come across a solution or a workaround.

How to in Verilog : pass a filename to be `included in the code using a parameter

Quick Digital simulations using UltraSim simulator in ADE-L

I recently had a situation, where I needed to check the correctness and obtain a rough estimate of the delay of my digital system design created using custom cells in Virtuoso. The custom cells were themselves created using gates and transistors. Now UltraSim in ADE is probably a very powerful simulator and can actually help the Analog designers figure out the appropriate parameters they need to set for their designs. However, I am not trying to tweak the parameters. I have already done that when creating the cells. I need to put those together and perform a quick simulation. This is where the speed and  sim_mode options come in handy.

If you are working with the GUI, then navigate to Simulation->Options->Analog and change the Simulation Mode to one of the Digital modes (Digital Extended, Digital Fast or Digital Accurate). I generally choose Digital Fast and modify the Speed Option to one of the Aggressive levels. I choose Aggressive (6). And then run the simulations as you normally do.

If you are more comfortable with Ocean scripts, then add the following lines anywhere before the run()command


option(
'speed "Aggressive (6)"
'sim_mode "Digital Fast (DF)"
)

 

Your simulations should run faster than they would run without these options and would generally be accurate enough if all you are concerned with are propagation delays.

Quick Digital simulations using UltraSim simulator in ADE-L

Patch connections in Virtuoso

Have you ever come across a situation where you have to connect a set of multi-bit wires with another set of multi-bit wires?

I have.

And I did not know how to connect them to each other. The problem was compounded by a requirement that one set of wires was named din<63:0> coming from one 64-bit input port. I had to connect this to a component in my schematic that had two 32-bit ports (D0 and D1). The wires had to alternate between these two ports. Thus din<63> was to be connected to D1<31>, din<62> to D0<31>, din<60> to D1<30> and so on.

I could not just short them together because then Virtuoso would complain. I spent two hours trying to figure out a solution and did not know what to search for on Google. That was until I came across the Virtuoso Schematic Composer user guide ( Yes! I should have looked at it first), that mentioned “patchcord” connections. So that is what it was called.

Went back to my schematic inserted the ‘patch’ cell from the ‘basic’ library and all done. This is what my schematic looks like now. The symbol that looks like a “patchcord” or a “jumper” is the patch…. of course.

patchcord_virtuoso_screenshot

But watch out, there is a catch.

Quoting fromAndrew Beckett’s answer on the Cadence Supportf forums at https://community.cadence.com/cadence_technology_forums/f/38/t/2792

You should be able to use patch from basic (or Add->Patchcord in the schematic editor) to alias nets. The patch component can alias both single (scalar) nets and bus/bundle (vector) nets. The one thing you can’t do is to alias two different terminals, two different global nets, or a terminal to a global net. For that, you can use the “cds_thru” component in basic. cds_thru ends up as something equivalent to a short in all the things it gets netlisted to – so for Verilog, it’s a true through connection (because you can do that in Verilog); for spectre it’s an “iprobe” (effectively a zero-volt source); for hspice it’s a zero-volt source; for VirtuosoXL it will get shorted by VXL because it has lxRemoveDevice on it; for CDL it ends up as a small resistor (which generally can be shorted by the physical verification tool); and for Diva it ends up as a component that can be removed using removeDevice() in your LVS rules.

That said, you should only use cds_thru for cases where patch can’t be used. patch is a direct alias in the database, so that’s better than introducing a real component in circuit simulators, say.

 

You can also use a single patchcord with a schematic patch expresssion “schPatchExpr”. The syntax for the same is

patch0_0

One needs to be careful with the nets that one is trying to connect through the patchcord connection. Quoting from the documentation

Only one of the nets can be connected to a schematic pin (I/O pin). Also, in the schematic editor, you cannot connect an input pin to an output pin even though you use a patchcord in the middle.

If you want to connect two pins together and rename them, the only way of doing this is to have a component in the way (such as basic/cds_thru, for example), You’d have to give the instance name of cds_thru I1<31:0> for example so that it has the same width as the bus. Note that cds_thru isn’t a true short – it’s designed for this kind of application though.

I learned it the hard way https://community.cadence.com/cadence_technology_forums/f/38/t/37566

 

Patch connections in Virtuoso