Verilog sensitivity

A characteristic of Hardware Description Languages(HDL) (either VHDL or Verilog) is their model of a Flip Flop or a Latch. This is also called as the event control structure by the Verilog LRM. This is a structure that is not available in other programming languages that are not event driven.

The structure has a sensitivity list which indicates the signals that would trigger the actions described in the structure.  The actions modify the value/state of one or more signals and there could be different actions based on the value of other signals in the system. The conditions could use some of the signals specified in the sensitivity list. Now all this may sound very confusing, but people in the trade generally use or come across these constructs countless times.

In verilog the structure when used to describe a F/F is written as


always @(posedge clk or negedge rst_n)
begin
	if (~rst_n)
	begin
		a<= 1'b0;
		b <= 5'b00000;
	end
	else if ((en == 1'b1) && (c == 4'b0101))
	begin
		a <= 1'b1;
		b <= 5'b10101;
	end
	else
	begin
		a<= 1'b0;
		b <= 5'b00000;
	end
end

Now an interesting consideration here is that for signals that are in the sensitivity list, the value that is used to test within the conditions such as

 if (~rst_n) 

is the value that the rst_n signal takes after the event control block is triggered.

However the value of the signal ‘c’ that is used in the test condition is the one that it has “setup time” before the trigger occurs and not the value of ‘c’ after the trigger. Thus if ‘c’ is changing in a separate event control block from 4’b0010 to 4’b0101 on the same clock edge that the above event control block is triggered, then the second condition would not be evaluated to ‘true’. Instead it will continue using the old value of ‘c’. If ‘en’ remains high for one more clock cycle, then the new value of ‘c’ (4’b0101) would be used and the value of the signals ‘a’ and ‘b’ would change to 1’b1 and 5’b10101 on the next clock edge.

Now personally I find the response of the event control structure to changes in ‘c’ in accordance with real hardware. This is because in a real device, if ‘c’ is changing on a certain clock edge, then the new value would be available to the destination F/F only after a certain finite time. This time is the total of the clock-to-Q of the source F/F and the propagation delay of the wire from source to destination F/F. And taking into consideration this delay and the clock skew, in most cases, it is not possible for the new value of ‘c’ to be available before the setup time of the destination F/F.

This is an interesting behaviour that is difficult to get your head around. However once you manage to understand this correctly, working with HDLs becomes a lot easier.

 

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Verilog sensitivity

How to in Verilog : pass a filename to be `included in the code using a parameter

Is there any way to pass a parameter to `include? I’m trying to do the
following

parameter DEFFILE = “file.txt”;

`include DEFFILE;

This gives me errors though…. Anyone have any ideas?

Unfortunately there does not seem to be a solution for this issue. This is because in Verilog, the `include is handled by the pre-preocessor which parses the files even before the compiler can have a go at it. The parameter on the other hand are examined during elaboration. 😦

This discussion was originally found at http://compgroups.net/comp.lang.verilog/pass-parameter-to-include/2118239. It was noticed because I was also trying to do something similar. Will update this post, when I come across a solution or a workaround.

How to in Verilog : pass a filename to be `included in the code using a parameter

Quick Digital simulations using UltraSim simulator in ADE-L

I recently had a situation, where I needed to check the correctness and obtain a rough estimate of the delay of my digital system design created using custom cells in Virtuoso. The custom cells were themselves created using gates and transistors. Now UltraSim in ADE is probably a very powerful simulator and can actually help the Analog designers figure out the appropriate parameters they need to set for their designs. However, I am not trying to tweak the parameters. I have already done that when creating the cells. I need to put those together and perform a quick simulation. This is where the speed and  sim_mode options come in handy.

If you are working with the GUI, then navigate to Simulation->Options->Analog and change the Simulation Mode to one of the Digital modes (Digital Extended, Digital Fast or Digital Accurate). I generally choose Digital Fast and modify the Speed Option to one of the Aggressive levels. I choose Aggressive (6). And then run the simulations as you normally do.

If you are more comfortable with Ocean scripts, then add the following lines anywhere before the run()command


option(
'speed "Aggressive (6)"
'sim_mode "Digital Fast (DF)"
)

 

Your simulations should run faster than they would run without these options and would generally be accurate enough if all you are concerned with are propagation delays.

Quick Digital simulations using UltraSim simulator in ADE-L

Patch connections in Virtuoso

Have you ever come across a situation where you have to connect a set of multi-bit wires with another set of multi-bit wires?

I have.

And I did not know how to connect them to each other. The problem was compounded by a requirement that one set of wires was named din<63:0> coming from one 64-bit input port. I had to connect this to a component in my schematic that had two 32-bit ports (D0 and D1). The wires had to alternate between these two ports. Thus din<63> was to be connected to D1<31>, din<62> to D0<31>, din<60> to D1<30> and so on.

I could not just short them together because then Virtuoso would complain. I spent two hours trying to figure out a solution and did not know what to search for on Google. That was until I came across the Virtuoso Schematic Composer user guide ( Yes! I should have looked at it first), that mentioned “patchcord” connections. So that is what it was called.

Went back to my schematic inserted the ‘patch’ cell from the ‘basic’ library and all done. This is what my schematic looks like now. The symbol that looks like a “patchcord” or a “jumper” is the patch…. of course.

patchcord_virtuoso_screenshot

But watch out, there is a catch.

Quoting fromAndrew Beckett’s answer on the Cadence Supportf forums at https://community.cadence.com/cadence_technology_forums/f/38/t/2792

You should be able to use patch from basic (or Add->Patchcord in the schematic editor) to alias nets. The patch component can alias both single (scalar) nets and bus/bundle (vector) nets. The one thing you can’t do is to alias two different terminals, two different global nets, or a terminal to a global net. For that, you can use the “cds_thru” component in basic. cds_thru ends up as something equivalent to a short in all the things it gets netlisted to – so for Verilog, it’s a true through connection (because you can do that in Verilog); for spectre it’s an “iprobe” (effectively a zero-volt source); for hspice it’s a zero-volt source; for VirtuosoXL it will get shorted by VXL because it has lxRemoveDevice on it; for CDL it ends up as a small resistor (which generally can be shorted by the physical verification tool); and for Diva it ends up as a component that can be removed using removeDevice() in your LVS rules.

That said, you should only use cds_thru for cases where patch can’t be used. patch is a direct alias in the database, so that’s better than introducing a real component in circuit simulators, say.

 

You can also use a single patchcord with a schematic patch expresssion “schPatchExpr”. The syntax for the same is

patch0_0

One needs to be careful with the nets that one is trying to connect through the patchcord connection. Quoting from the documentation

Only one of the nets can be connected to a schematic pin (I/O pin). Also, in the schematic editor, you cannot connect an input pin to an output pin even though you use a patchcord in the middle.

If you want to connect two pins together and rename them, the only way of doing this is to have a component in the way (such as basic/cds_thru, for example), You’d have to give the instance name of cds_thru I1<31:0> for example so that it has the same width as the bus. Note that cds_thru isn’t a true short – it’s designed for this kind of application though.

I learned it the hard way https://community.cadence.com/cadence_technology_forums/f/38/t/37566

 

Patch connections in Virtuoso

Ubuntu 16.04 and Windows 10 dual boot – grub not showing up while booting

Life was going on as usual. I had Windows 10 (I am not going to bother trying to find out if it is Pro, Home or Enterprise or whatever it is called) installed on a Lenovo Z50 laptop. My work as an academic researcher demanded that I also have Linux. So enter Ubuntu 16.04 and the pains associated with maintaining a dual-boot system. A couple of months after I had stored a solid chunk of my work on the Ubuntu partition, my laptop suddenly decides that it does not want to boot into Ubuntu. I do not see the grub splash screen at power on and go straight into Windows. Searching around on DuckDuckGo (yes I know ‘google’ is a verb now, but I am sceptical) threw up some answers. The most common amongst them was to run a command on the Windows command prompt

bcdedit /set {bootmgr} path \EFI\ubuntu\grubx64.efi

Unfortunately that did not seem to help me. Thankfully I found an answer in a post on https://tutorialsformyparents.com/how-i-dual-booted-linux-mint-alongside-windows-10-on-a-uefi-system/

Somewhere down where the author talks about UEFI and boot managers, I found my clue. The idea is that in addition to Devices that one can boot from, there now exist options that allow the user to select, which boot manager to select. With Windows 10 and some Micrium Recovery tool that I had installed on my Laptop, the Windows boot manager had somehow been given preference and it would not detect Ubuntu that had been installed later. So now I had to go and figure out, how to do the same on my laptop. None of F9/F6/F5 keys would take me into the Boot Options menu.

This is where Stackexchange came to the rescue. Lenovo Z50 and some of the other laptops in that series have a “Novo” button (how creative with the name) that is defined as

enter image description here

So then I shut down my Laptop, pressed the “Novo” button and select Boot Menu.

IMAG0569.jpg

I then reorder the boot managers so that Ubuntu is on top,

IMAG0570.jpg

Save and Exit and voila! my grub splash screen is back and I am able to boot into Ubuntu.

Lessons learnt

  1. Dual boot is tricky but doable
  2. There is goodness and a lot of good people in this world
  3. googling (sorry I meant searching) helps

 

Ubuntu 16.04 and Windows 10 dual boot – grub not showing up while booting

Citation key not visible in Mendeley – What should I do?

There are situations in your publishing career, where you have a few thousand references that you need to wade through, and cite in your document. For those of us using Latex and Bibtex to create their wonderful research papers, the bib files have a field called the citation key. Now in most cases, the citation key is the Author Name followed by the year. But if your library has grown really large and is synced in multiple places, the citation key sometimes have some funny suffixes. So now instead of a key called “Dabholkar2015”, you would have a key “Dabholkar2015a”. For those using Mendeley and Overleaf as their library manager and Latex editor respectively, the problem is compounded because Mendeley auto-generates the .bib file that you include in Overleaf. Now, since everything is in the “cloud” and “auto-sync”ed, you do not have any way of editing the .bib file in Overleaf. On top of that, Mendeley regenerates the .bib file every time there is a change and so any manual edits you make to the .bib file in your Overleaf project would be lost, the next time, the Mendeley library is refreshed.
Unfortunately, Mendeley have decided that citation keys should not be visible by default, so you have to turn them on. Here I’ll copy from an answer I found on StackExchange : Go to the menu->Tools->Options->Document Details, then choose the document type (for instance, Journal Article), then check the Citation Key box. Then, a field for Citation Key should be visible in the details pane on the right hand side of the window.Options Box Document Pane

Citation key not visible in Mendeley – What should I do?

wget files of a certain type from multiple folders on a website

A common requirement when one is trying to download log files archived on some websites is that one needs logs from a particular date each month or from a specific date, but from all machines where the logging is being carried out.

I recently faced such a situation. I was trying to download the route views from the Packet Clearing House website. This website archives router dumps from various locations worldwide and uploads them to their server neatly arranged under various folders.

The content is organised as follows.

Home => Resources => Routing Data => IPV4 Daily Snapshots => <Year> => <Month> => <Route Location> => <Route_filename.Year.month.date.gz>

Now I needed the routing data from all locations, for 2017.04.01, so I used ‘wget‘ that is commonly available in almost all Linux installations to get the files. The wget command I used was

wget -r --accept "*.04.01.gz*" --level 2 "https://www.pch.net/resources/Routing_Data/IPv4_daily_snapshots/2017/04/"
wget files of a certain type from multiple folders on a website